Some row-address-decoders used with static field effect transistor memories have the serial combination of a load resistor (typically a depletion transistor) and a plurality of enhancement address decoder transistors. For proper operation, the ohmic value of the load resistor is selected to be high relative to the resistance of each of the enhancement transistors. The total resistance of the load resistor and any one of the enhancement transistors is selected to be relatively high in order to keep power dissipation relatively low. This results in output voltage rise times that are slower than is desirable in some applications in which capacitance loads must be driven. Decreasing the ohmic value of the load resistor and enhancement transistor improves rise time, but at the expense of a considerable increase in power dissipation. The trade-off between improved rise time and increased power dissipation is not favorable in some applications.
It would be desirable to have a row-address-decoder circuit which has a driver stage that can provide relatively fast operation with relatively low power dissipation and output voltage logic levels which are close to or at the potential levels of power supplies used with the circuit.